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| application note TEA2028 - tea2029 an407/0594 by : j-m. merval & b. d'halluin summary page TEA2028 i general description ............................................... 3 ii main functions ..................................................... 4 iii pin connection (TEA2028b) . . . . . . . . . . . . . . . . . . . . . . . ................... 4 iv internal block diagram ........................................... 5 v functional description ............................................ 6 v.1 internal voltage and current references . ....... ................ 6 v.1.1 1.26v voltage reference . . . . . . . . . ....................................... 6 v.1.1.1 generator block diagram. . . . . . ......................................... 6 v.1.2 current reference. . . . . . . . . . . . . ......................................... 6 v.2 line sync. extraction . .......................... ................... 6 v.2.1 black level locking . . . . . . . . . . . ......................................... 7 v.2.1.1 application. . . . ............. ......................................... 7 v.2.2 memorizing the sync pulse 50% value . . . . . . . . . . . . . . . . . . ................... 8 v.2.2.1 i c i d ratio calculation . . . . . . . . . . . . ....................................... 8 v.2.3 sync pulse detection . . . . . . . . . . ......................................... 9 v.3 first phase locked-loop stage o f 1o................................. 9 v.3.1 phase locked-loop o f 1o block diagram . .................................... 9 v.3.2 functional duty of individual blocks . . . . . . . . . . . ............................. 10 v.3.2.1 phase comparator. ................................................... 10 v.3.2.2 low-pass filter . . . . ................................................... 10 v.3.2.3 vco centered on 500khz . ............................................. 10 v.3.2.4 divider stage . . . . . ................................................... 10 v.3.3 functional description of building blocks . . . . . . . . . . . . . . . . . ................... 10 v.3.3.1 phase comparator o f 1o................................................ 10 v.3.3.2 low-pass filter . . . . ................................................... 11 v.3.3.3 vco (voltage controlled oscillator) . . . . . . . . . ............................. 11 a. 503khz ceramic filter. . .......................... ................... 11 b. simplified block diagram of vco . . . . . . . . . ............................. 12 c. characteristics of the external filter . . . . . . . . . . .......................... 12 d. study of the internal amplifier . . . . . . . . . . . . . . . . . . . . . . ................... 13 e. characteristics of the non-linear amplifier oa4o . . . . . . . . . ................... 14 f. voltage-frequency transfer characteristics of vco . . . . . . . . . . . . . . . . . . ....... 14 v.3.4 o f 1o time constant switching .......................... ................... 14 v.3.5 video identification stage . . . . . . . . . ....................................... 15 v.3.5.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . ............................. 15 v.3.6 characteristics of loop f 1................................................ 15 v.3.6.1 locking accuracy. . . . . . . . . . . . . . . . . . . . . . . . ............................. 15 v.3.6.2 dynamic study. . . . . . . . . . . . . . ......................................... 16 a. long time constant . ................................................ 16 b. short time constant . ............................. ................... 16 v.3.7 phase comparator inhibition. .......................... ................... 17 1/46
v.4 line saw-tooth generator . . . . . . . . . . . . . . . . . . . . . . ................... 18 v.5 second phase locked loop o f 2o..................................... 19 v.5.1 duty of different building blocks. . ......................................... 20 v.5.1.1 o f 2o phase comparator . . . . . . . ......................................... 20 v.5.1.2 low-pass filter . . . . ................................................... 20 v.5.1.3 phase modulator . . . . . . . . . . . . . . ....................................... 20 v.5.1.4 flip-flop . . . . . . ...................................................... 20 v.5.1.5 output stage . . . . . . . . . . . . . . . . . ....................................... 20 v.5.1.6 line deflection stage . . . . . . . . . . . ....................................... 20 v.5.2 operation of building blocks . . . . . . . ....................................... 20 v.5.2.1 phase comparator o f 2o................................................ 20 v.5.2.2 low-pass filter f(p). .......... ......................................... 21 v.5.2.3 phase modulator . . . . . . . . . . . . . . ....................................... 21 v.5.2.4 line flip-flop (TEA2028 only) . . . . . . . . . . . . . . . ............................. 21 a. block diagram. . . . . . . . . . . . . . . . . . . . . . . . ............................. 22 b. t10 calculation . ................................................... 22 c. 16ms window . . . . . . . . . . . . . . . . . . . . . . . . ............................. 22 d. auto-set to o1o . . . . . . . . . . . . . . . . . . . . . . . . ............................. 22 e. maximum ot10o value as a function of oc1o . . . . .......... ................ 22 v.5.2.5 line output stage & inhibitions . . . . . . . . . . . . . ............................. 22 a. inhibition at start-up. . . . . . . . . . . . . . . . . . . . ............................. 23 b. inhibition during line flyback . . . . . . . . . . . . . ............................. 23 c. safety inhibition . . . . . . . . . . . . . . . . . . . . . . . ............................. 23 v.5.2.6 line deflection stage . . . . . . . . . . . ....................................... 23 v.5.3 characteristics of loop o f 2o .............................................. 25 v.5.3.1 study of the static error . . . . . . . ......................................... 25 a. phase shift error in case of no adjustment . . ............................. 25 b. study of shift adjustment . . . . ......................................... 26 v.6 vertical deflection driver stage . . . . . . . . . . . . . . .................... 26 v.6.1 frame sync extraction . . . . . . . . . . . . . . . . . . . . . ............................. 27 v.6.2 frame saw-tooth generator . ............................................. 27 v.6.2.1 60hz standard switching . . . . . . . . ....................................... 28 v.6.3 functions of frame logic block . . . . ....................................... 28 v.6.3.1 50/60hz standard recognition . . . . . . . . . . . . . . . . . . . . . . . . ................... 29 a. 50hz standard recognition . . . ....................................... 29 b. 60hz standard recognition . . . ....................................... 29 v.6.3.2 vertical synchronization window - free-running period. ....................... 29 v.6.3.3 frame blanking signal . . . . . . . . ......................................... 30 v.6.3.4 frame blanking safety (TEA2028 only) . . . . . . . ............................. 30 v.7 switching power supply driver stage . . . . . . . . . . ................... 31 v.7.1 power supply block diagram . . . . . . . . . . . . . . . . ............................. 31 v.7.2 general operating principles . . . . . . ....................................... 32 v.7.3 electrical characteristics of the internal regulation loop . . . . . ................... 32 v.7.4 power supply soft-start . . . . . . . . . . . . . . . . . . . . ............................. 33 v.7.5 protection features. . . . . . . . . . . . ......................................... 34 v.7.6 tv power supply in standby mode . . . . . . . . . . . ............................. 34 v.7.6.1 regulation by primary controller circuit . . . . . . . ............................. 34 v.7.6.2 regulation by TEA2028 . . . . . . . . ....................................... 34 v.8 miscellaneous functions . . . ....................................... 35 v.8.1 super sandcastle signal generator . ....................................... 35 v.8.2 video and 50/60hz standard recognition output . . . . . . ....................... 35 vi TEA2028 application diagram ....................................... 36 TEA2028 - tea2029 application note 2/46 tea2029 vii tea2029 : differences with TEA2028 ................................. 37 vii.1 general. . . . . . . . . . . . . . . . . . . . . ....................... ................ 37 vii.2 pin by pin differences . ............................................. 37 vii.3 tea2029c pin connextions . . . . . . . . . . . . . .......... ................... 37 vii.4 frame phase modulator. . . ......................................... 37 vii.5 frame blanking safety . . . . . . . . . . . . . . . . ............................. 38 vii.6 on-chip line flip-flop. . .......................... ................... 39 vii.7 agc key pulse . . . ................................................... 40 viii application information on frame scanning in switched mode (tea2029 only) . . . . . . . ............................. 40 viii.1 fundamentals. . . ................................................... 40 viii.2 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . ................... 40 viii.3 typical frame modulator and frame output waveforms . . . . ....... 41 viii.4 frame power stage waveforms . . . . . . . . . . . . . . . . .................... 42 viii.5 frame flyback . . . . . . . . . . . . ......................................... 43 viii.6 feed-back circuit . . . . . . . . . . . ....................................... 43 viii.6.1 frame power in quasi-bridge configuration . . . . . ............................. 43 viii.6.1.1 choice of oro value . . . . . . . . . . ......................................... 43 viii.6.1.2 influence of r3 value. . . . . .......................... ................... 43 viii.6.1.3 oso correction circuit in quasi-bridge configuration . . . . . . . . . . . . . . . . . . . . ....... 44 viii.6.2 frame scanning in switched mode using coupling capacitor . . . . . . . . . . . . . ....... 44 viii.6.3 frame safety. . . . ............. ......................................... 45 viii.7 frame scanning in class b (with flyback generator) . . . . . . . . ....... 45 viii.7.1 application diagram . . . . . . . . . . . . . . . . . . . . . . . ............................. 45 ix tea2029 application diagram complete application with tea2164 ... 46 i - general description as depicted in figure 1, the TEA2028 combines 3 major functions of a tv set as follows : - horizontal (line) and vertical (frame) time base generation for spot deviation. the video signal is used for the synchronization of both time bases. - on-chip switching power supply controller syn- chronized on line frequency. this integrated circuit has been implemented in bipolar i 2 l technology, and various functions are digitally processed. in fact, resorting to logic func- tions has the advantage of working with pure and accurate signals while full benefit is drawn from high integration of logic gates (approx. 110 gates per mm 2 ). the main objective is to drive all functions using an accurate time base generated by a master 500khz oscillator. also, horizontal and vertical time bases, are ob- tained by binary division of reference frequency. this has the advantage of eliminating the 2 adjust- ments which were necessary in former devices. one section of this integrated circuit is designed to drive a switching power supply of recent implemen- tation called omaster-slaveo. switching takes place on the primary side (i.e., directly on mains) of a transformer. the device ensures smps control , start-up and protection functions. control signals go through a small pulse transformer thereby pro- viding full isolation from mains supply. this new approach fully eliminates the bulky mains transformers used in the past. in addition, it offers optimized power consumption and reduction of tv cost-price. TEA2028 - tea2029 application note 3/46 ii - main functions - detection and extraction of line and frame syn- chronization pulses from the composite video signal. - horizontal scanning control and synchronization by two phase-locked loop devices. - video identification. - 50 or 60hz standard recognition for vertical scan- ning. - generation of a self-synchronized frame saw- tooth for 50/60hz standards. - line time constant switching for vcr operation through an input labeled ovcro (video cassette recorder). - control and regulation of a primary-connected switching power supply by on-chip controller de- vice combining : ? an error amplifier ? a pulse width modulator synchronized on line frequency ? a start-up and protection system - overall tv set protection input - frame blanking and super sandcastle output sig- nals - frame blanking safety input for crt protection in case of vertical stage failure. iii - pin connections pin description 1 horizontal output monostable capacitor 2 frame blanking safety input 3 frame saw-tooth output 4 frame blanking output 5 frame ramp generator 6 power ground miscellaneous functions sync separator horizontal time base vertical time base horizontal power amp. vertical power amp. smps controller TEA2028b miscellaneous power supplies primary connected smps miscellaneous power supplies mains input video signal uhf i.f. separator sound i.f. picture i.f. sound detection picture detection uhf color decoding rgb 2028b-05.eps figure 1 pin description 7 smps control output 8 supply voltage (v cc ) 9 smps regulation input 10 horizontal output 11 super-sandcastle output 12 horizontal flyback input 13 horizontal saw-tooth generator 14 current reference 15 smps soft-start and safety time constant capacitor 16 f 2 phase comparator capacitor (and horizontal phase adjustment) 17 v co phase shift network 18 v co output 19 v co input 20 frame sync time constant adjustment capacitor 21 substrate ground 22 f 1 phase comparator capacitor 23 vcr switching input 24 video and 50/60hz identification output (mute) 25 video identification capacitor 26 horizontal sync detection capacitor (50% of peak to peak sync level) 27 video input 28 safety input dip28.eps package : dip28 TEA2028 - tea2029 application note 4/46 2028b-02.eps figure 2 iv - internal block diagram 26 27 24 25 h. sync 50/60hz muting output 23 22 vcr switching input safety input 28 1.26v v r 20 21 substrat ground subst 1.26v v r 16 14 19 17 18 15 12 13 11 h. output 10 9 h. inhibit 8 s.m.p.s. output 7 1.26v v r 1 2 5 3 frame blank output 2 m s frame error amplifier 50/60 hz 503khz video input frame sawtooth output frame sawtooth h. sawtooth generator horizontal flyback input 3.3k w v cc horizontal output s sc output 6 vco 500khz v cc power ground 4 v cc frame blanking output frame blanking safety frame sawtooth output video identification vcr input j 1 inhibition time constant switching j 1 det horizontal synchro and frame synchro safety logic frame safety s.m.p.s. j modulat. super sandcastle reference current voltage j 2 line monostable horizontal logic timing frame timing identificationlogic 50/60hz switch on/off safety circuit soft starting circuit TEA2028b TEA2028 - tea2029 application note 5/46 v - functional description majority of the on-chip analog functions were com- puter simulated and results such as temperature variation, technological characteristic dispersion and stability, have led to the enhancement and implementation of actually employed structures. a parallel in-depth study of the device implemented in form of integrated sub-sections is provided to analyze the overall performance in a tv set. v.1 - internal voltage and current references v.1.1 - 1.26v voltage reference for optimum operation of the device, an accurate and temperature-stable voltage generator inde- pendent from v cc variations is used (band-gap type generator). the generated 1.26v is particularly used as refer- ence setting on input comparators. v.1.1.1 - generator block diagram v be i t v be l a l generator -2mv/ c t +0.086mv/ c dt dv o =0 v o v be =+a . l = 1.26v s 2028b-06.eps figure 3 with l = k ? t q = 25.7mv at + 25 o c d l dt = k q = + 0.086mv/ o c dv be dt = v be ( 25' ) - 1.26 t = - 2mv/ o c if a l = 1.26 - v be then : v o = 1.26v (temperature-independant) in practice, maximum drift due to temperature can be + 0.23mv/ o c i.e., 1.5% for a d tof80 o c. 14 v v be1 be2 1.26v i ref i 14 r ext v cc + band gap 3.32k w 1% 2028b-07.eps figure 4 v.1.2 - current reference this is implemented using the 1.26v generator in combination with an external resistor. i ref i 14 = v 14 r ext = 1.26 + v be1 - v be2 r exy let's i 14 = i and v eb1 =v be2 then : i ref = 1.26 r ext = 380 m a thus, it follows that i ref is accurate and inde- pendent of both v cc and temperature. a set of current generators proportional to i ref current are used in various circuit blocks. v.2 - line sync. extraction horizontal and vertical time bases should be syn- chronized with corresponding sync. pulses trans- mitted inside the infra-black portion of video signal. the duty of this stage is to extract these sync pulses. the output signal, called composite sync, contains the vertical sync which is transmitted by simple inversion of line sync. pulses. the vertical sync pulse is then extracted from this composite signal. the main advantage of this arrangement is its ability to operate at video input signal levels falling within 0.2v to 3v peak-to-peak range and at any average value. the operating principle is to lock the black level of the input signal (pin 27) onto internaly fixed voltage (v n ) and then memorize the average voltage of the sync pulse by using an integrating capacitor con- nected to pin 26. finally, the composite sync signal is delivered by a comparator the inputs of which are driven by v 50% and video signals. TEA2028 - tea2029 application note 6/46 sync level t s' v pp black level video input signal composite sync. output signal t h t r frame sync. 2028b-08.eps figure 5 v.2.1 - black level locking 27 cc v + i c + i d i d = constant i c v n =2v v s1 v p v c27 v pp c1 -14 v n =2v i c video 2028b-09.eps figure 6 the video signal is applied to pin 27 through the coupling capacitor oc27o. since the sync pulse amplitude is generallyequal to 1/3 of v pp (i.e. 66mv to 1v) and in order to obtain a good precision of the black level, the sync pulse should be amplified by a coefficient of - 14 before being applied to the comparator oc1o. this comparator will charge the oc27o capacitor as long as v s1 >v n ? v s1 will stabilize at v n during the line flyback interval ot r o if the average charge of oc27o capacitor is nil for one t h period. i c /i d is calculated such that the locking occurs at the middle of the back porch. 0 t t v s1 i c -5 m a t s t r v s1 v n (2v) t 1 t r t s = 2 + t s 2028b-10.eps figure 7 the d v s1 producedby i d during the line trace which is : 14 ? i d ? t a c27 must be equal to d v s1 during the time interval ot1o, i.e. : 14 ? i c ? t 1 c27 it follows that : i c i d = t a t 1 = t h - t r t s + t r - t s 2 substituting t h =64 m s, t r =12 m s, t s = 4.7 m s (which are standard and constant values) into above equation : i c i d = 6.23v v.2.1.1 - application at i c =5 m a ? i d =31 m a - with c27 = 220nf, d v s will be 14 ? 5 ? 52 220 = 16mv which yields 0.8% maximum error in black level with respect to v n = 2v at the beginning of retrace time - due to transposition on amplifier stage, the black level voltage on pin 27 is equal to 2v. TEA2028 - tea2029 application note 7/46 - in practice, at low amplitude video signals, it is recommended to insert a low-pass filter before the oc27o capacitor so as to attenuate the chromi- nance sub-carrier and the noise components. the aim is to reduce the phase variations of the detected sync pulse and thus enhance the hori- zontal scanning stability. 27 220nf 1k w 100pf 1k w cc v + chroma burst 2028b-11.eps figure 8 v.2.2 - memorizing the sync pulse 50% value the objective is to memorize the voltage corre- sponding to 50% of the line sync pulse v s1 by using an external capacitor connected to pin 26 (see figure 9). the overall arrangement comprises two compara- tors. - comparator c2 : delivers an output voltage ov1o by comparing v s1 +v d ,v 26 and the voltage drop across two resistors. - comparator c3 : which delivers a constant output current thereby maintaining on capacitor oc26o, the voltage v 50% corresponding to 50% of peak to peak sync pulse. during the line scanning, diode odo is reverse bi- ased : v s1 +v d =v 1 v.2.3 - sync pulse detection this function is fulfilled by comparing the inverted video signal (v s1 +v d ) whose black level is con- stant at 2v, with the sync 50% voltage level on pin 26 (see figure 10). comparator c4 will deliver the line sync pulse (ls) which will be used for 3 functions : - horizontal scanning frequency locking : output to j 1 phase comparator. - frame sync extraction for vertical scanning syn- chronization. - detecting the presence of a video signal at circuit input. the ls signal in two latter functions is filtered for noise by using combination of current generator i and a zener diode equivalent to a capacitor. using this extraction technique at a very noisy video signal yields remarkable display stability. the device also provides for scanning synchroni- zation at aerial signal attenuation of approximately 75db, i.e. 15 to 20db better than other sync proc- essors. v.3 - first phase locked-loop stage o j 1o this stage is commonly called the first phase locked-loop o j 1o. its duty is to lock the frequency and the phase of the horizontal time base with respect to the line sync signal. in the absence of transmission (i.e. lack of line sync), the horizontal scanning frequency is ob- tained by dividing the output frequency of a vco device. this vco oscillates at approximately 500khz and uses a low frequency drift ceramic resonator. this method eliminates the need of hori- zontal frequency adjustment. 26 v 50% c4 v 50% vv + s1 d v + cc + 3v frame separator i i i + ls c ls on video recognition output v + cc 250ns ls video at pin 27 line sync. output toward phase comparator j 1 2028b-13.eps figure 10 v.3.1 - phase locked-loop o j 1o block diagram a (ma/rd) low-pass filter f(p) by-32-divider stages vco b (khz/v) 1 p + - dj i phase comparator w s horizontal frequency ceramic resonator f in f out ls j 1 v e w 1 2028b-14.eps figure 11 TEA2028 - tea2029 application note 9/46 v.3.2 - functional duty of individual blocks v.3.2.1 - phase comparator the duty of this comparator is to issue an output current proportional to the phase difference be- tween f in and f out . v.3.2.2 - low-pass filter this filter suppresses the parasitic component con- taining the sum of phases, smoothens the phase difference component and determines the timing characteristics of the loop. v.3.2.3 - vco centered on 500khz this is a voltage-controlled oscillator which gener- ates an output frequency proportional to the volt- age applied to its input. this voltage is delivered by low-pass filter. v.3.2.4 - divider stage it is used to divide the vco frequency (500khz) by 32 so that it can be compared with the line sync signal frequency of 15625hz. v.3.3 - functional description of building blocks v.3.3.1 - phase comparator o f 1o the comparator is functionally equivalent to a sig- nal multiplier (see figure 12). let's assume that : -i ls = i sin ( w h t+ f in ) and v f 1 = k cos ( w h t+ f out ) then : - i= i ls ? k 2 [ sin ( f in - f out ) + sin (2 w h t+ f in + f out )] (see figure 13) - the low-pass filter will suppress the 2f h frequency component - f in - f out difference being low : sin ( f in - f out ) f in - f out - the output current will be therefore proportionalto the phase difference between the signals com- pared. in other words, the average current over one period is : i av ? t h =i ? ? ? t s 2 + d t ? ? ? -i ? ? ? t s 2 - d t ? ? ? =2i d t i av =2i d t t h and d t= df t h 2 p the comparator conversion gain is thus : a= i df = i p (in a/rd) later in our discussion we shall consider the two possible values of the current i. for the time being, let's define these values as follows : - i = 500 m a for olong time constanto or normal operation - i = 1.5ma for oshort time constanto vcr mode or synchronization search (mute). the values of a are therefore : -a long = 0.16ma/rd -a short = 0.47ma/rd use of comparator inhibition signal is quite useful under noisy transmission conditions. it eliminates risk of incorrect comparison during the line scan- ning phase which would be due to the noise present on ls signal. horizontal phase and image stability are thus highly enhanced. characteristics of this inhibition signal will be dis- cussed at the end of this chapter. i v + cc 1.26v i ls i 2i 1ma 500 m a & ls long j 1 inhibition 1 mute vcr video recognition vcr mode switching f out 1.26v v j 1 signal f in v f i i o ls = 1 t h t s 0 d t i+ i- 2028b-15.eps figure 12 TEA2028 - tea2029 application note 10/46 t t t i t s i ls v j 1 i 0 0 +1 -1 i+ i- j e j out 2028b-16.eps figure 13 v.3.3.2 - low-pass filter (see figure 14) its main function is to reject the 2f h (31khz) fre- quency component delivered by the phase compa- rator. it also defines the characteristics of the loop in transient mode. the filter is built around two sub-sections which determine the stability and the response time of the loop in the following modes of transmission : normal or vcr modes. see section v.3.6 ody- namic study of f 1o. 22 r1 4.7k w c1 2.2 m f 10nf v i 5.6v vco stage i r1 c1 c r v vco j 1 comparator c 2028b-17.eps figure 14 r is the dynamic input resistance of the vco. the filter transfer function may be defined as fol- lows : - f(p) = v i = z(p) - z(p) = r 1 + r1 c1 p 1 + p ( rc + r1 c1 + rc1 )+ r r1 c c1 p 2 the second order terms of the denominator can be converted to first order products as a function of frequency as follow : f(jf) = r 1 + j f f1 ? ? ? 1 + j f f2 ? ? ? ? ? ? 1 + j f f3 ? ? ? with r1 = 4.7k w , r = 500k w , c1 = 2.2 m f, c = 10nf we obtain : -f1= 1 2 p r1 c1 = 15.4hz -f2= 1 2 p( r c1 + rc + r1 c1 ) = 0.14hz - f3 = 3.43khz f f f 2 f 1 f 3 (log scale) 0.14hz 15.4hz 3.43khz 0 0 arg (z) 20 log r 20 log |f| p 2 2028b-18.eps figure 15 v.3.3.3 - vco (voltage controlled oscillator) its function is to generate a frequency proportional to a control voltage issued externally, by the low- pass filter in our case. the period of the output signal is used as timing reference for various functions such as, horizontal and vertical time bases. the frequency range must be short and accurate : - it must be short since the power dissipated within the horizontal scanning block is inversely propor- tional to the line frequency. - the accuracy is required if the adjustment is to be omitted. the basic arrangement is to employ a ceramic resonator (or ceramic filter) which has quite stable characteristics as a function of frequency. a filter whose resonating frequency is a multiple of line frequency (15625hz) is to be selected. an example is 32 ? 15625 = 500khz. a. 503khz ceramic filter symbol 2028b-19.eps figure 16 r1 l1 c1 c0 equivalent circuit 2028b-20.eps figure 17 TEA2028 - tea2029 application note 11/46 where : r1 = 7 w , l1 = 1.26mh, c1 = 78pf, c0 = 507pf - series resonance frequency : f s = 1 2 p `````` l1 c1 = 503khz - parallel resonance frequency : f p =f s ? ``` 1 + c1 c0 = 540khz - tolerance within the resonance area : 503khz 0.3 % - temperature stability : 0.3% of f o at d t = 100 o c b - simplified block diagram of vco the overall arrangement is equivalentto a variable- phase amplifier configured in closed loop with the external passive filter. the system will oscillate if the open-loop gain is 0db and if v out leads v in . in closed-loop oscillating mode, the phase variation of v 18 /v in imposed by v 22 will result in same v out /v 18 variation but of opposite sign. this phase change will finally correspond to a change in frequency. c. - characteristics of the external filter the ceramic resonator behaves as a capacitor at f thus, a variable (24 o to + 135 o ) phase lead with a gain higher than 10db, must be implemented on- chip so as to enable the system to enter into oscillation. the frequencydead points correspond to the maxi- mum internal phase variations. this phase shift is controlled by voltage v 22 whose value of 5.6v 0.7 is determined by two diodes. from the figure 21, the non-linearity of phase-fre- quency characteristics is clearly apparent. if linear voltage-frequency response is required for a sym- metrical gain of f 1 loop, it would then be necessary to implement a non-linearity, on the phase control amplifier a4, but in the opposite direction. d. - study of the internal amplifier let's study the gain and phase response of v 18 v in as a function of v 22 . v 22 = v c k where k is a non-linear coefficient to start with, the ov c o voltage of comparator oa3o is taken as reference parameter. the dynamic representation of the output stage can be depicted as below (figure 22). with : i 2 '= i 2 1 + j w r1 c1 (at f = 500khz) r1 c1 w =1 ? i 2 '= i 2 1 + j and z = r1 + 1 j w c << r ? i i 2 ' r1c1 network produces -45 o phase lag of oio with respect to oi2o, around 500khz. v 18 -r ? (i 1 +i 2 ') i 1 and i 2 calculation as a function of ov in o on pin 19 - a1 amplifier : v s1 v in = r c dr 1 = 1200 57 =21 dr : dynamic resistance = l i - a2 amplifier : i 2 v s2 = 1 2dr 2 = 1 54 ? i 2 v in = v s1 v in ? i 2 v s1 = 0.395 ? i 2 = 0.39 v in ,i 2 is in phase with v in therefore : i 3 =-i 2 = -0.39 v in - a3 amplifier : i 1 =i 3 ? ? ? - v c a l + 1 2 ? ? ? = - 0.39 v in ? ? ? - v c a l + 1 2 ? ? ? 17 18 1 i 2 i v 18 r i 18 c1 r1 17 18 1 i v 18 r i 18 i z 2 i' 2028b-25.eps figure 22 v 18 @i 1 =0 v in v out phase variation = f(v c ) v 18 @i 1 (max. ) ri 1 ri 2 v in -45 r(i + i ) 12 r(i + i ) 12 +136 2028b-26.eps figure 23 : vector representation of v 18 /v in ov in o always leads the oi 1 o by 180, only the ampli- tude of i 1 is a function of v c (see figure 23). - v out v in =- r i 1 ( 1 + jr 1 c 1 w ) + i 2 1 + j ( r 1 + r ) c 1 w -i 1 = - 0.39 v in ? ? ? i 2 - v c 4 l ? ? ? and i 2 = 0.39 v in the figure 24 illustrates the characteristics of v 18 /v in phase versus v c . - phase variation determined by v c falls between +24 o and +135 o range - the gain is higher than 10db. the pin 18 output signal of 30 to 40db has a rectangularcomponent (see figure 24). TEA2028 - tea2029 application note 13/46 0 40 80 120 160 200 20 30 40 f v out / v in (degrees) -200 -150 -100 -50 0 50 100 v c (mv) a a j v in v 18 (db) 20 log 2028b-27.eps figure 24 e - characteristics of the non-linear amplifier oa4o (see figures 25 and 26) this is a differential amplifier whose equivalent feed-back resistors of emitters vary as a function of its input voltage. the maximum output voltage swing is set by two oclampo diodes connected to ov 22 o input. f - voltage-frequency transfer characteristics of v co (see figure 27) the transfer characteristic is linear and centered at 5.6v at 500khz operating frequency. t transfer = d f d v = 22.4kh/vz and once it goes through five divide-by-two stages : t = 22.4 32 = 0.7khz/v -150 -100 -50 0 50 100 5 5.5 6 6.5 7 v (mv) c 22 v (v) a = 25mv/v a = 50mv/v a= 300mv/v 2028b-28.eps figure 25 : v c = f(v 22 ) 0.7 0.6 0.5 0.4 55.66 6.5 i ( m a) 22 v(v) 22 =33m w dv 22 di 22 = 500k w dv 22 di 22 = 820k w dv 22 di 22 2028b-29.eps figure 26 : i 22 = f(v 22 ) 480 500 520 4567 pin 18 frequency (khz) 518khz t = 22.4khz/v pin 22 voltage o v 22 o(v) 2028b-30.eps figure 27 v. 3.4. - o f 1o time constant switching when switching between stations or receiving sig- nal via a vcr, the loop locking interval must be as short as possible so as to avoid unwanted visible effect on the picture. in fact, since the synchroniza- tion between the vcr motor drive and the play- back head is rather imperfect, it will produce frequency and phase fluctuations in the output composite video signal. under these conditions, phase locking interval must be oshorto (vcr mode). in the case of broadcast transmission, this loop must also filter all phase variations produced by noisy sync signal. in this case, its locking time constant must be olongo (normal mode). in other ojungleo circuits, this time constant switch- ing is carried out by capacitor switching within the filter loop. in our case, this function is achieved by changing the current amplitude of the phase com- parator. TEA2028 - tea2029 application note 14/46 this amplitude changing modifies the open-loop system gain and therefore the damping coefficient and the locking time constant. the device will be in short time constant mode under the following two conditions : - vcr mode or scart connector mode : this mode is enabled by a low state on pin 23. v 23 < 2.1v. - transmitter search and tunning. in order to accelerate the capture, a ovideo iden- tificationo stage will detect the presence or the absence of a video signal on input pin 27, and deliver accordingly a signal called omuteo. v.3.5 - video identification stage this stage will detect the coincidence between the line sync pulse (if present) and a 2 m s pulse issued from the logic block. this 2 m s pulse at line fre- quency is positionned at the center of line sync pulse when the first loop o j 1o is locked. this sampled detection is stored by an external capacitor connected to pin 25. the video recogni- tion status is also available on pin 24 so as to enable sound muting during station search proc- ess and the inhibition of automatic frequency tun- ing. v.3.5.1 - block diagram 25 i c 750 m a i d 500 m a + c25 4.7nf i c(25) pin 24 frame logic j 1 comparator 4.6v & & ls ls 2 m s 2028b-31.eps figure 28 the video recognition signal is delivered by a hys- teresis comparator. the recognition time ot r o is adjustable by an exter- nal capacitor, as soon as j 1 is locked : -i c25(av) =i c ? 2 m s 64 m s and : -t r = c25 ? v h i c25 ( av ) = 1.96 ? 10 5 ? c25 with c25 = 4.7nf ? t r = 1ms (which is clearly quite fast) with video without video v = 0.3v hyst i c(25) i c mute output line sync. ls i d 0 1 j 1 v h v l 4.6v 2 m s v 25 i c(25) 2 m s 4.7 m s 2028b-32.eps figure 29 v.3.6 - characteristics of loop f 1 v.3.6.1 - locking accuracy let's study the phase error o j out - j in o under steady state conditions : the open-loop gain is : - t(p) = ab f ( p ) f where : a = 0.16ma/rd (long time constant) a = 0.47ma/rd (short time constant) b = 0.7khz/v or b = 4.4 10 3 rd/s - f(p) = r ? 1 +t 1 p ( 1 + t 2 p )( 1 +t 3 p ) where : r = dynamic input resistance of vco. if a phase step of dj is applied to the input, the following would be obtained as a function of (p) : f in ( p ) = df p using the last value theorem : lim f(t) = lim p . f(p) let's calculate lim p 0 ( j in - j out ) - the closed-loop gain is : - h(p) = t ( p ) 1 + t ( p ) = abf ( p ) p + abf ( p ) = f out ( p ) f in ( p ) that is : lim p 0 p (f in -f out )= lim p -> 0 p d f p + ab f ( 0 ) 0 TEA2028 - tea2029 application note 15/46 it is therefore deduced that the system can follow all input phase variations without producing any static error. in practice, there will be a slight error due to the input bias current oi b o of vco, which is 0.55 m aat f o = 500khz. this dc current is delivered by a phase comparator which will generate a phase error of : - long time constant : df long = i b a long = 0.55 ? 10 - 3 0.16 = 3.4 ? 10 -3 rd or 35ns in d t - short time constant : df short = i b a short = 12ns these two errors cause a horizontal picture dis- placement. on a large screen of 54cm wide, this will be : 64 - 12 = 52 m s, which for both modes corresponds to a shift of : d line = df long -d f short 52 ? 520 = 0.24mm it is obvious that such displacement can be fully neglected. response to a frequency step - the input phase is : f in (t) = dw t which as a function of (p) is : f in (p) = dw p 2 - the accuracy is : lim p -> 0 ( f in -f out )= lim p -> 0 dw p + abf ( o ) = d w abr where r = 500k w at f(o) in this case, the phase error depends on both, the magnitude of the frequency step and the static gain abr. in general, d f d f which is the open-loop static gain, is taken into consideration. dw df = abr = 2 pd f d t 2 p =a ? 2 p ? b' ? r ? d f d t =ab'r ? 2 p t h (b' in khz/v) - in normal mode : a long = 0.16 ma/rd ? d f d t = 5.5khz/ m s, r = 500k w - in vcr mode : a short = 0.47 ma/rd ? d f d t = 16.5khz/ m s note : the capture range is specified within 500hz with respect to 15625hz. numerical example let's suppose that in vcr mode there is a fre- quency variation of 100hz, this will yield a phase variation of 0.1/16.5, i.e. 6ns which, on a 54cm wide screen, will produce a horizontal shift of d line = 0.06mm ! it is obvious that an excellent image stability is thus obtained. v.3.6.2 - dynamic study the loop response in transient mode is quite im- portant. it determines the overall system stability and the phase recovery time, which are imposed by the external filter of(p)o. the close-loop transfer function is equivalent to a second order system. these time constants are in practice displayed on screen by a bar delivered by a special pattern generator representing the phase errors. the following optimizedresults were obtained from filter f(p) connected to pin 22. filter component values are : r1 = 4.7k w , c1 = 2.2 m f, c = 10nf a. long time constant -at d tof4 m s ? n=18 lines, i.e. t long = 1.15ms. system oscillations are perfectly damped. image stability with a noisy video signal is very satisfac- tory. b. short time constant -at d t=4 m s ? n = 5 lines, i.e. t short = 0.32ms - n = 5 lines one should notice fast phase recovery, naturally followed by bounced oscillations due to the char- acteristics of a second order device. as given in application diagram section 6, an other alternative would be to use the following compo- nent values : r1 = 3.9k w , c1 = 4.7 m f, c = 15nf. TEA2028 - tea2029 application note 16/46 v.3.7 - phase comparator inhibition the phase comparator is disabled under two con- ditions : - during frame sync pulse (see figure 30) inverting the line sync pulse contained within the video signal will provide the frame sync pulses required for the synchronization of vertical scan- ning. since the current supply to comparator f 1is controlled by the line sync pulse, the comparator must be inhibited at the time of line sync inver- sions so as to avoid occurence of phase errors at the beginning of each frame. this inhibition is activated during fri (frame retrace inhibition) issued by frame logic circuitry. if f 1 is locked before the vertical scanning syn- chronization occurs, (e.g. when switching be- tween channels), and since fri phase is not yet correctly positioned, the j 1 must be further inhib- ited by fs signal which is the extracted frame sync pulse. - during line scanning (see figures 31 and 32) this inhibition will eliminate the occurrence of all possible phase errors due to a noisy sync signal or parasitics during the line scanning phase. it yields excellent display stability at noisy video signals. ? f1 inhibition in long time constant mode (vcr = 0) s inh(long) = mute . (fri + fs + blk . line inh ) and s inh(short) =1 inhibition is activated during, frame sync, fri and each time line trace interval - except at frame beginning between lines 8 and 21. ? f 1 inhibition in short time constant mode (vcr = 1) s inh(short) = mute . (fri + fs) = s inh(long) in vcr mode, inhibition is disabled during line trace since phase or frequency variations are not taken into account instantenously. +4 m s-4 m s shift - 4 m s n n normal mode long time constant vcr mode short time constant +4 m s n 2028b-33.eps figure 30 : on screen display of time constants inverted pulses for frame sync. in the abscence of frame inhibition inhibition video composite sync. frame sync. (fs) frame j 1 inhibition (fr) frame blanking s inhibition (normal mode) j 1 comparator current j 1 inhibition signal (fri + fs) [vcr mode] 2028b-34.eps figure 31 TEA2028 - tea2029 application note 17/46 v.4 - line saw-tooth generator before going through a detailedstudy of the second phase locked loop o f 2o, let's have an overview of the linesaw-tooth generator which has been mainly implemented for f 2 phase variations and also the phase modulation of the switching power supply. it uses the combination of an external capacitor connected to pin 13 and an internally implemented constant current generatorto generatea saw-tooth voltage at line frequency. its frequency is determined by the reset frequency of the capacitor oc13o. this reset signal is issued by the line logic circuitry at a period multiple of vco period ( 32). -i c =k ? i r =k ? 1.26 r 14 = 200 m a -v 13pp = i c ( t h - t reset ) c13 = k ? 1.26 ( t h - t reset ) r14 ? c13 = 3.48v -v ce(sat)t1 20mv ? v 13(max) = 3.5v - in sync mode : t h =64 m s, t reset = 6.5 m s, k = 0.527 2% 13 14 xk i r r14 3.32k w c13 3.3nf constant 1.26v i r i c v + cc reset to j 2 and smps x1 t1 reset 6.5 m s 64 m s t h v 13 v pp 3.5 0t t 2028b-37.eps figure 34 0.3 m s 2.35 m s 2.35 m s 5.8 m s 6.5 m s inhibit ion inhibition line sync . j 1signal video on pin 27 line inhibiti on 2028b-35.eps figure 32 100 m a (short) 500 m a (long) j 1 & & & line sync. ls phase comparator ( j 1) s inh(s) inh(l) s & 1 video recognition mute fri & fs line inhibition blk vcr 2028b-36.eps figure 33 : j 1 inhibition logic block diagram TEA2028 - tea2029 application note 18/46 turn-off delay 12 m s64 m s blanking time center of screen line transistor collector current t lf saturation turn-off line transistor control output line flyback line yoke current video signal on cathodes 0 0 2028b-38.eps figure 35 1 10 12 a ma/ m s i d t j 2 phase comparator t' out phase modulator v 16 f(p) low-pass filter monostable (29 m s) horizontal phase adjustment output stage (x 1) inhibition t out line yoke eht transformer line deflection stage x1 lf pulse shaping lf t out t' out 29 m s constant delay by j 1 j 2 signal video (pin 27) t in line flyback 2028b-39.eps figure 36 : second phase locked loop o j 2o block diagram v.5 - second phase locked loop o f 2o this stage controls the horizontal deflection of the electron beam i.e., the horizontal picture scanning. the frequency of operation, in the absence of video signal, is a multiple of the vco frequency, i.e. 15625hz - 500hz. when video signal is present, the scanning fre- quency is synchronized with the video signal through the first phase locked-loop o f1 o. the output rectangular waveform signal drives the line switching transistor. this transistor, when turned-off, generates what is commonly called the oline flybacko. in order to obtain a horizontally centered picture, the line flyback (lf) must coincidewith the blanking time on tube cathodes. the turn-off delay is due to transistor base storage time. this time varies in different tv sets as the transistors employed may have different operating characteristics which are functions of temperature variations, power rating and base drive. therefore, it follows that in order to obtain stable image centering, the line flyback must be phase- locked with respect to the video signal. the second phase-locked loop also offers the pos- sibility of horizontal phase-shift adjustment. TEA2028 - tea2029 application note 19/46 v.5.1 - duty of different building blocks v.5.1.1 - o f 2o phase comparator this block generates a current proportional to the phase difference between the phase reference o f2 o and the middle of the line flyback to be phase- locked. v.5.1.2 - low-pass filter - rejects the parasitic component osum of phaseso - smoothens the ophase differenceo component - allow ophase adjustmento by generating an error within the loop v.5.1.3 - phase modulator uses the line saw-tooth voltage to convert the voltage delivered by the low-pass filter into a phase corresponding to the line transistor turn-off control signal. v.5.1.4 - flip-flop generates the turn-off control signal for a constant time (fixed by the external capacitor), the phase of which is set by the modulator. v.5.1.5 - output stage - delivers the control signal for line transistor driver - disables the output during start-up and protection phases v.5.1.6 - line deflection stage - generates the saw-tooth current for line yoke - generates the high voltage required by picture tube and other supply voltages the line flyback information is provided by the eht transformer. v.5.2 - operation of building blocks to provide an easier understanding of the subject, the o f2 o loop study will be covered as a function of various time intervals and not as a function of phase. v.5.2.1 - phase comparator o f 2o the operation is identical to that of o f1 o loop. the v f2 signal issued by logic block is phased with respect to the middle of line sync pulse on pin 27 and delayed by a 2.6 m s interval so as to be at the middle of blanking time on video cathodes. the output current component o2f h o is rejected by the low-pass filter. v cc v j 2 i constant voltage filter f(p) i 550 m a line flyback (lf) 2028b-40.eps figure 37 - the average current is i = 2i d t t h where : d t=t in -t out - the conversion gain is therefore : a= i d t = 2i t h =17 m a/ m s at : i = 550 m a and t h =64 m s, oao will remain constant since oio is a multiple of oi ref o current on pin 14. 0.3 m s 2.6 m s videp on pin 27 video on cathodes lf d t 0 +i -i i t h t out t in v j 1 v j 2 2028b-41.eps figure 38 TEA2028 - tea2029 application note 20/46 v.5.2.2 - low-pass filter f(p) the horizontal phase-shift adjustment is taken into account : see figure 39 - filter v = f(i) transfer characteristic is given as : v = zi + z r ? k ? v cc -z ? i in where : ? z=r in // r // 1 c ? p ? r in ,i in : modulator input characteristics 16 r in i in phase modulator v v cc + c p kv cc horizontal phase adjust r i j 2 comparator 2028b-42.eps figure 39 in dynamic mode -v=zi ? f(p) = v i = z(p) = r 1 +t p where : ? r' = r in // r (r >> potentiometer p) ? t = r' . c : filter time constant the network behaves as a first order low-pass filter whose cut-off frequency at -3db is : f -3db = 1 2 p r c filter component values - r = 470k w and c = 22nf ? in practice, (k [0,1]) v cc = 12v -r in = 25m w ,i in = 0.65 m a (base input current) ? f - 3db = 15.7hz with adjustment and 0.3hz with- out adjustment v.5.2.3 - phase modulator this is built around a comparator which converts the filter voltage to a rectangular waveform such that its rising edge phase, variable as a function of filter voltage ovo, will trigger the line transistor turn- off control circuitry. the conversion gain is determined by the slope of the line saw-tooth applied to comparator. 16 t' out v' out v v 13 (t) 2028b-43.eps figure 40 v 13 (t) t 1 = f(v) t 2 v' out v j 2 t d t' out t out =0 t in 3.5v 0 line output signal (pin 10) line flyback (lf) v t in( j 2) t h t 10 = constant 2028b-44.eps figure 41 transfer characteristic is given by : d t out d v = d t 13 d v 13 = b = 16.4 m s/v therefore t 2 = b.v let's consider the delay interval between ot out o and the reference time ot in o where t out is the middle of line flyback : t out -t in =t 2 +t d +t 1 -t h where : - t1 = 4.3 m s reset for v 13 and v f2 are signals coming from line logic block and are synchronized on line sync -t d = 2 to 15 m s delay between leading edge of output signal - pin 10 - and the middle of line flyback -t h =64 m s -t out -t in = b.v + t d - 59.7 m s v.5.2.4 - line flip-flop (TEA2028 only for tea2029 refer to section vii.6) it generates a constant duration rectangular signal used to turn-off the line transistor. it is triggered by the rising-edge of the phase comparator output voltage and reset after capacitor on pin 1 is charged. TEA2028 - tea2029 application note 21/46 a. block diagram ov' out o will set the flip-flop thereby allowing the capacitor oc1o to be charged by current oi c o deliv- ered through current generator. the voltage across capacitor begins rising until it reaches ov ref o. at this time, comparator oco is triggered, the output of which will in turn reset the flip-flop. the capacitor oco is consequently discharged by current i d -i c . 1 & 1 s rq q v ref c1 v 1 + i c 144 m a i d 380 m a 16 m s as auto-set signal v 10 to output stage t' out t 10 t' out v' out window c 2028b-45.eps figure 42 b. t10 calculation (see figure 43) t 10 = c1 ? d v 1 i c = c1 ? v ref i c oi c o is a fraction of oi ref o on pin 14 i c = i ref a = v ref a ? r14 = 144 m a ? t 10 = a ? r14 ? c1 = 2.64 ? r14 ? c1 with r14 = 3.32k w , c1 = 3.3nf ? t 10 =29 m s -t 10 is independent from temperature and v cc - a has a maximum dispersion of 3% from device to device c. 16 m s window this window is generated by the line logic circuitry and sets the maximum phase variations of the output signal ov 10 o. also, for protection purposes, should ov 16 o voltage equal o0o, the output signal will be always present and have a maximum phase shift of 16 m s with respect to the falling-edge of the line saw-tooth. d. auto-set to o1o to provide protection, this function will trigger the flip-flop if the modulator is disabled, i.e. v 16 >v 13(max) . maximum phase variation t v ref (1.26v) 0 v' v out 1 4 m s auto-set set window 16 m s 16 m s t 10 t 10 t 10 v 10 2028b-46.eps figure 43 e. maximum ot10o value as a function of oc1o t 10 (min.) :16 m s (window) + 4 m s (auto set) = 20 m s ? c1 (min.) = 2.3nf t 10 (max.) : for c1 ? v ref i d - i c + c1 ? v ref i c 64 m s ? t 10 (max.) =40 m s ? c1 (max.) = 4.6nf for normal operation, c1 value has to be chosen between 2.3nf and 4.6nf. if pin 1 is grounded, output signal (pin 10) is inhibited and goes high. v.5.2.5 - line output stage & inhibitions 1 10 6 12 i v r t 10 10 cc l + output to line odriveo 3v line flyback input lf t 10 monostable q 1 logic 1 for v cc <6v logic 1 for security at pin 28 inhibition power ground 2028b-44.eps figure 44 TEA2028 - tea2029 application note 22/46 open-collector output : v 10(sat) < 1.5v at i 10(max) = 20ma the line output (pin 10) will go high if either the following three inhibitions is activated : a. inhibition at start-up this is generated by a hysteresis comparator which is driven by okv cc o and the o1.26vo reference voltage. this inhibition is mandatory since the device will operate only at v cc 5v. v hyst = 0.5v 1 0 5.5 6 supply voltage (v) line inhibition (logic level) 2028b-48.eps figure 45 b. inhibition during line flyback the output signal pin 10 is high during line transis- tor turn-off. the leading edge of output signal pin 10 turns off the line transistor after a delay interval (storage time). the line transistor turn-off generates an overvol- tage on the collector corresponding to the line flyback pulse. during this interval, in order to avoid transistor destruction, the pin 10 output must ab- solutely remain high. this is done internally with the line flyback pulse (pin 12), which forces pin 10 output to high level during the line flyback time. c. safety inhibition the device has a security input terminal opin 28o. if a signal lower than v ref (1.26v) is applied to this pin, line and power supply outputs are all inhibited. this function is particularly useful for tv chassis protection. refer to section v.7.5 for further details. v.5.2.6 - line deflection stage this chapter will cover a general description of the ohorizontal deflection stageo employed almost commonly in all recent tv sets. deflection of electron beam is proportional to the intensity of magnetic field induced by the line yoke. this yoke is equivalent to an inductor. the deflec- tion is therefore proportional to the current through inductor. in order to obtain a linear deflection from left to right as a function of time, a saw-tooth current must be generated within the yoke. the approachis toapply a switched dc voltage to the line yoke. - when k is closed : i l(t) = e r y ? ? ? 1 - e - ryt l ? ? ? - l r y is always higher than half of trace time : t trace 2 = t h - t lf 2 = 64 - 12 2 =26 m s -oi l o variations as a function of time : c k e i l(t) r y deflection yoke resistance deflection yoke inductance (l) 2028b-49.eps figure 46 di l dt = e l e - ryt l e l ? ? ? for t < < l r y ? ? ? the current will therefore be linear as a function of time i l(t) = e l ? t from ot 1 otoot 2 o which is the second portion of the line trace interval. - current at the end of trace : i m = e l ? t trace 2 - energy stored within inductor : w = 1 2 ? l ? i m 2 if the switch is opened at t = t 2 , the ol.co combi- nation will enter into oscillation, the energy stored within inductor is transfered to the capacitor, which will return it to the inductor and so on. the circuit period is classically given by : t=2 p ? ``` lc if oko is closed at time ot 3 o, the inductor will once again have a voltage oeo across its terminals. the current falls linearly until ot 4 o. this phase corre- sponds to the first half of line trace interval. the overvoltage across c is : v p =e t trace 2 ``` lc + e during t lf p ``` lc that is : v p =e t trace ? p 2t lf +e in practice, e is higher than 100v. t trace =52 m s, t lf =12 m s ? v p 780v note that this overvoltage is almost 8 times higher than the source voltage oeo. this overvoltage is applied to the primary winding of a ostep-up trans- formero (eht transformer) in order to generate the high voltage required by picture tube anode. TEA2028 - tea2029 application note 23/46 0 i l i k v c v l t lf e v p i c end of trace begining of trace if k remains open t3 t4 t1 t2 0 0 0 0 e 2028b-50.eps figure 47 in practice, the power switch oko is built by a combination of ohigh voltage switching transistoro and ofast recovery diodeo. if considered in average value, it is seen that the voltage across capacitorocso is almost equalto the source voltage oeo. the saw-tooth current through this capacitor will produce a parabolicripple around oeo, which will thus modify the equivalent source of the line yoke and induce a modified current of oso shape within the yoke. this oso current is used to produce a linear picture as a function of the picture tube geometry. the basic arrangement can be reconstructed by assuming that the equivalent inductor olo is the transformer ol p o and line yoke inductors put in parallel (since vc s(av ) = e). the output pin 10 of TEA2028 is applied to a matching stage called oline drivero the output of which drives the power transistor ot r o. the match- ing stage is necessary for optimized base drive. at middle of trace, the transistor enters into satura- tion and its current rises linearly. v 10 will then issue a control signal to turn the transistor off. the tran- sistor will be in fact turned-off after a delay interval ot s o (storage time) varying from 2 to 8 m s depending on application. the system will then enter into oscillation during its half-period thereby generating the line flyback. at the end of flyback time, the line yoke current is negative while the voltage across capacitoroco has fallen to zero. the energy transfer automatically takes place by the recovery diode during the first portion of trace time. also, it is clear that the line scanning phase with respect to video signal is determined by the rising- edge of pin 10 output signal. 10 12 li ne flyba ck input l r coup ling capacitor t driver +12v tr i tr i c i d d v eht (anode) [15 to 25kv] miscellaneous power supplies line flyback (pin 12, TEA2028b) cc 5 v c(5) i y line yoke eht transformer e (regulated by smps) l p TEA2028b 2028b-51.eps figure 48 : simplified diagram of the horizontal deflection stage TEA2028 - tea2029 application note 24/46 t t t t t 12v (turn-off delay) t s t 10 12 m s 0 0 0 0 0 29 m s s correction i y v ce (tr) v 10 i tr i d tr c d c 2028b-52.eps figure 49 high level duration (t10) of pin 10 output signal must be higher than the delay interval ot s(max) o+ the flyback time (i.e. 8 + 12 = 20 m s) and must turn-off before the end of diode conduction : t 10 b. study of shift adjustment with r, p network connected to pin 16, the t out becomes : t out = - br i in 1 + t 2 + t d - 59.7 m s 1 + t 2 + b r r ? kv cc 1 + t 2 with : t2 = abr' (where r' = r // r in ) and k [0;1] substituting the following values into above equa- tion : - r = 470k w - r' = 470k w // 25m w = 46k w -a=17 10 -6 a/ m s -b=16 m s/v -t d =10 m s -t 2 = 125 -v cc = 12v -t out = - 38ns - 390ns + 1.5 m s k therefore t out = 1.5 ? k - 0.43 ( in m s) if k varies between 0 and 1 ? t out [- 0.43ms to 1.07 m s] which corresponds to a picture displacement of : d line [- 4mm to + 11mm]. shift variations as a function of v cc (with adjustment) dt out dv cc = b r r ? k 1 + t 2 b r r ? k t 2 k ar =k ? 0.12 m s/v dl dv cc = 0.34mm/v at k nominal = 0.28 therefore, a constant v cc must be applied to the potentiometer. v.6 - vertical deflection driver stage this stage must constantly drive the vertical spot deflection. such deflection will horizontallyscan the screen from top to bottom thus generating the displayed image. similar to horizontal deflection, the vertical deflection is obtained by magnetic field variations of a coil mounted on the picture tube. a saw-tooth current at frame frequency will go through this coil commonly called oframe yokeo. frame period is the time required for the entire screen to be scanned vertically. c.c.i.r. and n.t.s.c. tv standardsrequire respec- tively 50hz and 60hz frame scanning frequen- cies. also, a full screen display is obtained by two successivevertical scannings such that the second scanning is delayed by a half line period with respect to the first. this method increases the number of images per second (50 half images/s or 50 frames/s in 50hz standard). this scanning mode called ointerlaced scanningo eliminates the fliker which would have been otherwise produced by scanning 25 entire images per second. the circuit will generate a saw-tooth voltage which is linear as a function of time and called oframe saw-tootho. a power amplifier will deliver to the oframe yokeo a current proportional to this saw- tooth voltage. it is thus clear that this saw-tooth voltage reflects the function of the vertical spot deflection; which must itself be synchronized with the video signal. synchronization signals are ob- tained from an extraction stage which will extract the useful signal during line pulse inversion of the composite sync signal. synchronization occurs at the end of scanning, in other words, when the saw-tooth voltage at pin 5 is reset. this function is accomplished by the oframe logic circuitryo of full digital implementation. this processing method offers various advan- tages : - accurate free-running scanning frequency eliminates the frequency adjustment required by previous devices. - digital synchronization locked onto half line frequency thereby yielding perfect interlaced dis- play and excellent stability with noisy video signal. - automatic 50/60hz standard recognition and switching the corresponding display amplitude. - optimized synchronization in vcr mode. - generation of variousaccurate time intervals , such as narrow osync windowso thus reducing considerably the vertical image instability in case of for instance, mains interference,superimposed on frame sync pulse. - generation of vertical blanking signal for spot flyback and to protect the picture tube in case of scanning failure. TEA2028 - tea2029 application note 26/46 frame sync. separator 3 5 24 x1 50/60hz output frame sawtooth frame yoke v i i y power amplifier r5 c5 +e frame sawtooth generator i 60 50/60hz reset & 1 frame logic free reset h/2 reference block composite sync. i y top of picture bottom of picture t 2028b-54.eps figure 51 : block diagram of the vertical deflection stage v.6.1 - frame sync extraction the main duty of this stage is to extract the frame sync pulses contained in composite sync signal. i c i d + i c c v c frame sync. =2 m a =9 m a c = 35pf i c i c i d + 2.8v composite sync. 5.6v 2.8v 2028b-55.eps figure 52 : sync. extractor block diagram two current generators are used to charge and discharge the integrated capacitor oco. the dis- charge generator (i c +i d ) is driven by the compos- ite sync signal. the d v c across capacitor is : - i d ? t sync c during frame trace, the capacitor is discharged at each line sync pulse thereby generating a d vof -0.94v with respect to 5.6v and then recovers the charge by current oi c o. the comparator output re- mains low. the discharge time is 27 m s at the first line sync inversion applied to comparator input. the voltage ov c o then falls from 5.6v to 0.2v and triggers the comparator oc 0 o which will deliver a frame sync pulse when ov c o crosses the 2.8v level. the overall arrangement behaves as an integrator and will therefore suppress any noise susceptible to be present on input signal. an external capacitor pin 20 can be added to the integrated capacitor c to increase the frame sync time constant. v.6.2 - frame saw-tooth generator 3 5 frame sawtooth output r3 2.2k w c5 470nf r5 2.7m w + + +e (200v) 60hz frame reset (64 m s) frame logic block d i 60 2028b-56.eps figure 53 the frame saw-tooth is generated by an external rc network on pin 5. the time constant or5 ? c5o is much higher than the frame period. therefore, the generated saw- tooth is quite linear. the network is discharged by an internal transistor, controlled by the frame logic block. TEA2028 - tea2029 application note 27/46 v 3 t 4.4v 1.26v v ref () 64 m s 20ms (50hz) 2028b-57.eps figure 54 v.6.2.1 - 60hz standard switching the ntsc standard requires a vertical picture scanning frequencyof 60hz, i.e. a saw-tooth period of 16.66ms. in order to obtain an identical deflection amplitude whatever the standard (50 or 60hz), the saw-tooth amplitude for both periods must be the same. 60hz standard recognition is performed automat- ically by the frame logic block, which will issue a signal to drive a current generator o d i 60 o. this current will be summed with the external charge current and will increase the saw-tooth slope, so as to yield same saw-tooth amplitude to that set in 50hz standard. this current is centered around 14 m a and is a fraction of i ref applied to pin 14. employing the recommended component values for network connected to pin 5, this current will result in identical amplitude in both standards. d v 5 = i 60 t 60 c 5 = i 50 t 50 c 5 ? i 60 = i 50 60 50 = 1.2 i 50 32 m s l625 l1 l2 l1 l2 lx tx frame sawtooth (pin 3) h/2 reset (counter) sync. 2028b-58.eps figure 55 i 50 = e r 5 = 200v 2.7m w = 74 m a ? i 60 = 88 m a therefore d i 60 =14 m a v.6.3 - functions of frame logic block this section is fully implemented by i 2 l logic gates. it is clocked by an accurate oh/2o clock running at half line period (32 m s). the required periods and time intervals are obtained by counting the clock pulses. for the sake of clarity, timing signals so obtained are labeled by the line number corresponding to video signal. the time corresponding to oxo scanned lines with respect to the beginning of frame saw-tooth (re- set) is therefore : t x =64 m s (x - 1) + 32 m s & 1 2-bit register (50hz) & 3-bit register (60hz) 50/60hz identification f 50hz sync window generator sync. window & & sync. digital sync. or direct sync. extracted frame sync. vcr video recognition (mute) vcr f 60hz 2 m s reset discharge flip-flop 64 m sor 48 m s (vcr) sawtooth generator capacitor discharge control d i 60 free-running frequency pulses miscellaneous functions frame blanking fri inhibition ( j 1) 64 m s reset h/2 (32 m s) q1 q10 32.768ms binary dividers sync. 2028b-59.eps figure 56 : block diagram TEA2028 - tea2029 application note 28/46 16 .66ms 20ms 50hz sync 60h z sync 15.773ms 17.696ms 19.744ms 20.128ms l247 l277 l309 l315 w r(60hz) w r(50hz) 2028b-60.eps figure 57 v.6.3.1 - 50/60hz standard recognition this function is performed by two shift registers which are loaded by sync pulses (if present) and if these pulses fall within the time interval specific to each standard. these intervals are called oregister windowso and labeled ow r (50)o and w r (60). a. 50hz standard recognition this identification is considered valid if two suces- sive sync pulses applied to 50hz shift register fall within the 50hz window ow r (50)o. at the time of synchronization capture, the first pulse will reset the counters. the second pulse, if present, will then trigger the 50hz identification 20ms later [i d (50) = 1]. the identification is not valid if two sucessive 50hz pulses are not detected. identification signal is also used to reduce the vertical synchronization window in 50hz standard thereby offering excellent noise immunity against noise susceptible to be present in sync signal and hence good display stability. b. - 60hz standard recognition this identification is validated after three sucessive sync pulses at 16.6 m s period have been detected. three pulses are necessary to ascertain the iden- tification prior to switching the saw-tooth amplitude. the identification signal [i d (60) = 1] is also used to reduce the synchronization window and, in case of one or two missing pulses close to 60hz, to set the free-running frequency. v.6.3.2 - vertical synchronization window - free-running period in the absence of sync pulse various free-running periods are specified. since vertical scanning must be always active, these free-running periods must be higher than those of 50 and 60hz standards so as to ensure synchronization. an other window, allowing synchronization only at the end of scanning, is also necessary. upon syn- chronization, this window will allow vertical flyback only at the bottom of screen. this window should be narrow for good noise immunity but also wide enough to yield, upon synchronization, a capture time unperceptible on screen. in our case, as long as no standard identification takes place the window will remain wide, and once one of the standards has been identified, the win- dow will be considerably reduced. in vcr mode, this window will be always wide since frame frequencies delivered in high-speed search, slow review and picture pause modes are very much variable and must be taken into considera- tion. in the absence of transmission (mute = 0), synchro- nization is disabled (so as to avoid incorrect syn- chronization due to noise) and the free-running frequency is around 50hz. this will eliminate the occurrence of picture overlay at the end of trace at a lower free-running frequency. register's window l247 l277 l309 l315 l361 50hz 60hz free-running period reset reset reset reset w r(60) w r(50) w r(wide) w r =0 mute = 1 mute = 1 mute = 1 no transmission (mute = 0) 50hz standard 60hz standard i d60 =1 i d50 =1 i d50 =0,i d60 =0 or vcr mode 2028b-61.eps figure 58 : definition of synchronization windows and free-running periods TEA2028 - tea2029 application note 29/46 maximum capture time the worst case capture time occurs when the first sync pulse just precedes the sync window. let's find the number of periods necessary for the capture to occur, i.e. tn = 0. ? n = t l - t w t l - t sync ,t l = 23ms , t w = 7.3ms - 50hz : the number of periods is 6 ? t capture(max) = 120ms - 60hz : the number of periods is 3 ? t capture(max) = 50ms v.6.3.3 - frame blanking signal this signal is necessay to blank the display during each frame flyback. it is triggered at the beginning of frame saw-tooth flyback. the duration of this signal is 1.344ms (or 21 lines). this oframe blankingo signal is available through pin 4 (TEA2028 only) which is an open-collector output. it is also present within the normalized super sand- castle signal on pin 11 (TEA2028 and tea2029). v.6.3.4 - frame blanking safety (TEA2028 only, for tea2029 refer to section vii.5) its duty is to protect the phosphor coating of picture tube in case of any problem with vertical deflection function such as scanning failure. a signal to monitor correct scanning is provided by the frame yoke and applied to pin 2. in case of any failure, all frame blanking outputs are disabled and go high thereby blanking the entire screen. during trace phase, the voltage across frame yoke has a parabolical shape due to the coupling capaci- tor in series with yoke. during frame flyback, the current through frame yoke must be rapidly in- verted. conventionally, a two-fold higher supply voltage is applied across the yoke. this will pro- duce an overvoltage called oflybacko. the safety monitoring status is detected on the falling-edge of flyback, i.e. at the beginning of scanning. a differentiator network is used to trans- mit only fast voltage variations. the required pulse is then compared to 1.26vlevel. frame blanking goes high in the absence of nega- tive pulse (zero deflection current) or if the pulse does not fall within the first 21 lines (exagerated over-scanning). frame sawtooth sync pulses wide window 0 t w t n t 2 t 1 =0 (capture) t l t sync 2028b-62.eps figure 59 12 m s 20 m s l22 l335 1.344ms (21 lines)* first frame second frame frame blanking (pin 4) * 24 lines for tea2029c 2028b-63.eps figure 60 TEA2028 - tea2029 application note 30/46 2 4 70 m a 1k w 100k w 1nf frame yoke 1.26v 1.26v s.s.c. (pin 11) frame blanking output (with safety) 1 & frame reset (2 m s) q r s frame blanking (no safety) 0 i 2 v 2 0.5v 1.26v 1/1k w -70 m a 1.9v 1/1k w input characteristics frame yoke current (1.26v) flyback v 2 2028b-64.eps figure 61 : block diagram v.7 - switching power supply driver stage switching takes place on the primary side (mains side) of a transformer by using tea2164 smps controller manufactured by sgs-thomson. required voltage values are obtained by rectifying different voltage outputs delivered through secon- dary windings. the horizontal deflection stage is powered by one of these outputs delivering around hundred volts. this voltage source must be regulated since any voltage fluctuation will yield variations of the hori- zontal display amplitude. the te2028 monitors this voltage and transmits the regulation signal to the primary controller cir- cuitry via a small pulse transformer. the charac- teristics of this regulation signal are directly related to the conduction period of switching transistor. v.7.1 - power supply block diagram 7 9 14 tea2164 12v line deflection stage mains input p a v ref 1.26v 13 m1 m2 x1 & 28 m s window start-up circuitry safety flip-flop 1.26v 15 28 135v TEA2028b line sawtooth 2028b-65.eps figure 62 TEA2028 - tea2029 application note 31/46 7 9 40 m a -1 t1 100pf i v i i 2 i dc i 1 v i d v v ref (1.26v) t out low-pass filter v v in 13 b a 2028b-66.eps figure 63 -1.9 m s/mv v in (pin 9) 28 m s 10 m s 1.26v 9.5mv 5.2mv t (pin 7) on 2028b-67.eps figure 64 : conduction periode (pin 7) versus input voltage (pin 9) 2 m s t on 28 m s (max.) 135v 0 secondary winding voltage secondary rectifier diode current primary current primary pulses v lf v 13 7 2028b-68.eps figure 65 v.7.2 - general operating principles a fraction of the 135v output voltage to be regu- lated is compared to the 1.26v reference voltage. resulting error signal is amplified and then applied to phase modulator om 1 o, which will deliver a square waveform at line frequency whose duty cycle depends on the value of input voltage ov 9 o. a second phase modulator om 2 o will determine the conduction period as a function of voltage on pin 15. this function is mandatory for system start- up. a28 m s window is used to limit the conduction period of the primary-connected transistor. supply output (pin 7) and line output (pin 10) will be disabled if any information indicating abnormal operation is applied to safety input (pin 28). con- sequently, all power stages are disabled and the tv set is thus protected. v.7.3 - electrical characteristics of the internal regulation loop the phase modulator implemented by a simple transistor ot1o will compare in current mode, the image of amplified input (i 1 ) with saw-tooth current (i 2 ) at line frequency. with oi 2 o rising, as soon as the sum of oi 1 +i 2 -i dc o goes positive, the transistor enters into saturation thus determining the output conduction period. a low-pass filter implemented by combination of a 100pf capacitor and the input impedance of tran- sistor ot 1 o, attenuat es all frequency variations higher than the line frequency. - input amplification : a = di 1 dv in = 3.3 m a/mv - modulator conversion gain : b= dt out di 1 =- 0.558 m s / m a - overall gain of the internal loop : dt out dv in =- 1.9 m s/mv 1 1 + j f f 0 (f 0 = 15khz) smps waveforms for discontinous mode oflybacko configuration the primary-connected transistor is turned-off dur- ing the line flyback. all interference signals due to switching and sus- ceptible to affect the video signal will not therefore be visible on screen. regulation characteristics the following characteristics have been measured on a large screen and yield excellent results : - 135v voltage regulation as a function of mains voltage : better than 0.5% for mains voltage vari- ations of 170v rms to 270v rms (p = 60w at 135v) - 135 v voltage regulation as a function of load : better than 0.5% for a delivered power of 35w to 120w. this type of power supply offers the following ad- vantages : - overall efficiency enhancement: better than 80% - reduction of interferences by synchronizationon horizontal frequency TEA2028 - tea2029 application note 32/46 - full protection of the primary-connected transis- tor in case of short-circuit or open-load on secon- dary terminals - can provide 1w to 7w, for tv standby mode operation (refer to tea2164 application note). v.7.4 - power supply soft-start when the tv set is initially turned on, control pulses are not yet available and consequently the control- ler block on primary side will impose a low-power transfer to the secondary winding. this power is produced by an intermittent switching mode called oburst modeo. as soon as the v cc supply to TEA2028b exceeds 6v level, line and smps outputs are enabled.since the filtering capactitors on secondary side cannot charge up instantaneously, the voltage to be regu- lated would not yet be at its nominal value. without conduction period limitation upon start-up, the de- vice will set a maximum cycle of 28 m s which will result in a high current flow through the primary winding and thus through the switching transistor which will in turn activate the protection function implemented on primary side. consequently, the primary controller block will be inhibited and the set will not turn-on. a start-up system has been implemented within TEA2028b to overcome this problem. this soft start system, will upon initial start-up, use the image of the falling voltage on pin 15 to in- crease progressively the conduction cycle. the phase modulator om2o compares this voltage with line saw-tooth voltage and delivers the correspond- ing limitation cycle. during supply voltage rising cycle [v cc (pin 8) < 6v], the capacitor pin 15 will charge up rapidly while the voltage across it follows v cc . at v cc 6v, the capacitor is discharged via an internal current generator and the voltage across it decays linearly. at v 15 3.5v (line saw-tooth peak-to-peak volt- age), phase comparator om2o delivers a low con- duction period which will gradually increase. the conduction period (pin 7) will rise until the secondary voltage reaches the value set by poten- tiometer opo. when this occurs, the loop is acti- vated. the pin 15 discharge current value is 100 m afora duration of 2 m s line frequency. therefore i d ( av ) = 100 2 64 = 3.1 m a conduction period limitation voltage (pin 15) t on(lim) =56 m s-16xv 15 (in m s) 5.5v 5.5v 12v 6 6 3.5 t t t t v cc v c c v c c soft-start area regulated mode active area pin 8 supply voltage (v) pin 15 voltage (v) smps control output voltage (pin 7) line output voltage (pin 10)* * lin e output (pin 10) an d thyristo rco ntrol output (pin 4) for tea2029c 2028b-69.eps figure 66 TEA2028 - tea2029 application note 33/46 t on pin 15 voltage (v) 1.75 3.5 28 m s 2028b-70.eps figure 67 v.7.5 - protection features as soon as a safety signal (v 1.26v) is applied to pin 28, line and supply outputs (pins 10 and 7) are both disabled. capacitor oc15o begins charging up until the voltage across it reaches 4v (k ? v cc ). outputs are again enabled and conduction period gradually increases as it occurs upon initial start- up. the device will be definitively inhibited if the cycle of events is repeated 3 times. for the device to restart, the internal 3-bit register should be reset which requires the v cc to fall below 4v (see figure 68). pin 15 charging current : i c(av )=-i d(av) =-3.1 m a v.7.6 - tv power supply in standby mode v.7.6.1 - regulation by primary controller circuit this mode of regulation called oburst modeo is performed only by the primary controller circuit and is activated in the case of missing control pulses or in the absence of power supply to TEA2028b. in this mode, power available through secondary winding is limited. refer to tea2164 application note for further details. higher powers can be obtained by using the regu- lation feature offered by TEA2028b. in this case, the horizontal output (pin 10) must be disabled. v.7.6.2 - regulation by TEA2028 (see figure 69) in this case, all that is required is to disable the line scanning function thus reducing the overall power by 90%. the device power supply regulation loop remains active, for minimum conduction period to be 1.5ms the power delivered through secondary must be higher than 3w. line output inhibition two alternatives are possible : - grounding flip-flop pin 1 - apply a voltage higher than 3v to pin 12. t t t t 6v 3 2 i c i d full inhibition inverted for tea2029c 1.26 0 4 3.5 active area soft-start area pin 8 voltage (v) pin 15 voltage (v) pin 7 voltage pin 10 * voltage * line output (pin 10) and thyristor cont rol outpu t (pin 4) for tea2029c 2028b-71.eps figure 68 1 10 12 3v v l v 12 r1 r2 1 29 m s 10 v cc + standby mode 1.26v 1 lf line inhibition (standby mode) s r q 3.3nf 2028b-72.eps figure 69 TEA2028 - tea2029 application note 34/46 v.8 - miscellaneous functions v.8.1 - super sandcastle signal generator this signal used in video stage, is available on pin 11. it has 3 levels at specified time intervals : - 2.5v level used for vertical blanking at each frame flyback. its duration is 21 lines and is generated by the frame logic. this level will be maintained if vertical scanning failure is detected on pin 2. - 4.5v level used for horizontal blanking, its duration is deter- mined by comparing the line flyback signal on pin 12 to an internal voltage of 0.25v. - 10v level this signal is used by color decoding stage. its duration of 4 m s is determined by line logic cir- cuitry. with respect to the video signal on pin 27, this level is positioned such that it is used to sample the burst frequency transmitted just after the sync pulse. v.8.2 - video and 50/60hz standard recognition output a 3-level signal is available at pin 24 for video identification(mute) and for 50 and 60hz standards recognition. 24 v 24 cc v + cc v + mute r r 0 1 60hz 50hz 60hz standard without video 50hz standard /2 v cc v cc 0 v 24 transmit identification 2028b-74.eps figure 71 super sand castle (pin 11) 2.5v 4.5v 10v 4 m s line blanking (12 m s) frame blanking (21 lines) 4.7 m s 0.3 m s burst video signal (pin 27) 2028b-73.eps figure 70 TEA2028 - tea2029 application note 35/46 vi - TEA2028 application diagram 123 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 TEA2028b v cc 470 w 220 w 1.8k w 503khz 220 w 10 m f 150pf 22nf 1.5nf 10pf ground substrat 4.7nf vcr switch 10 m f 1k w 10nf 5.6k w v cc mute output 50hz/60hz identification 100nf 220nf video input v cc 10k w safety input 1.26v 3.3nf 2.2k w 3.32k w 47k w 3.3nf v cc 2.2nf 470k w lr 10 v pp v cc 10k w frame blanking output 2.7m w 470nf +200v 330 w to tea2161 1k w v cc 150k w 1k w 1k w smps output voltage adjust 100 m f super sand cast. 390 w 1k w 47nf line yoke 2mh - 2.5 w +200v +24v lf eht transformer +140v from smps transformer 7 1 2 5 6 3 tda8172 4 1nf pin 14 (TEA2028b) 33k w 13k w 150k w 100k w 1nf 680k w 15k w frame amplitudeadjust 100 w 100nf 470k w frame yoke 32 m h 15 w 0.7app 1 w 1000 m f 220 w vert. shift 2.2 w 100nf 1n4001 100 m f frame sawtooth safety input v ref +12v v cc 2028b-75.eps figure 72 TEA2028 - tea2029 application note 36/46 vii - tea2029 : differences with TEA2028 vii.1 - general the tea2029 has quite the same functions compared to TEA2028. the main difference is that the tea2029 incorporates a frame phase modulator intended to work with a switched mode vertical stage using a thyristor. the tea2029 can also be used with a linear vertical power amplifier such as the tda8170. vii.2 - pin by pin differences pin tea2029c TEA2028b 1 dfferential inputs of the frame error amplifier (including frame blanking safety in case of vertical stage failure). capacitor for horizontal output duration adjustment (29 m s typ. with c1 = 3.3nf) 2 vertical blanking safety input 4 frame output for thyristor control vertical blanking output (21 lines duration) 10 horizontal output (26 m s typ. duration) horizontal output (duration is adjustable) 11 supersandcastle output (with a frame blanking duration of 24 lines) supersandcastle output (with a frame blanking duration of 21 lines) 12 negative horizontal flyback input (115 v pp through a 47 k w resistor) positive horizontal flyback input (10v pp through a 47k w resistor) 20 positive agc key pulse output (low level when no video) capacitor for frame sync. time constant adjustment 28 safety input (inhibition of smps, horizontal and frame outputs when v 28 > 1.26v) safety input (inhibition of smps, horizontal outputs when v 28 < 1.26v) vii.3 - tea2029c pin connections pin description 1 frame error amplifier non-inverting input 2 frame error amplifier inverting input 3 frame saw-tooth output 4 frame output (for thyristor control) 5 frame ramp generator 6 power ground 7 smps control output 8 vcc supply voltage 9 smps regulation input 10 horizontal output 11 supersandcastle output 12 horizontal flyback input 13 horizontal saw-tooth generator 14 current reference 15 smps soft-start and safety time constant 16 f 2 phase comparator capacitor (and horizontal phase adjustment) 17 vco phase shift network 18 vco output 19 vco input 20 agc key pulse output 21 substrate ground 22 f 1 phase comparator capacitor 23 vcr switching input 24 video and 50/60hz identification output (mute) 25 video identification capacitor 26 horizontal sync detection capacitor (50% of peak to peak sync level) 27 video input 28 safety input dip28.eps package : dip28 vii.4 - frame phase modulator the tranconductance amplifier oa1o converts the differential input voltage into two output currents oi s1 o and oi s3 o. - a1 transconductance = i s1 v in =10 m a/mv - b transconductance = i s2 v 2 =40 m a/v - transfer characteristic = d t out d v in = 6.4 m s/v the filter time constant is maximum near the oper- ating point when i s1 @ i s2 in this case : - the base current of t 1 =oi s2 -i s1 o - the filter band-pass = 15khz the maximum conduction period of o40 m so is de- termined by the horizontal logic circuitry. the frame frame flyback is detected by transis- tor ot 3 o. there is no feed-back during frame flyback and oi s3 o is maximum (higher than i 4 ) which will drive the ot3o into conduction. TEA2028 - tea2029 application note 37/46 v i 1 2 4 v in transconductance amplifier i i s1 s3 i s2 t1 c 150pf i 4 t3 safety frame logic to super sand castle i.f. v i horizontal sawtooth 3.5v 64 m s frame output v cc 4.7k w & 1 s r q q safety & on/off switching voltage horizontal flyback phase limitation (horizontal logic) 40 m s b t out d 2028b-76.eps figure 73 t t 6 m s 40 m s max. v 13 v 4 3.5v 0 horizontal flyback frame output horizontal sawtooth 2028b-77.eps figure 74 vii.5 - frame blanking safety - during trace : i s3 i 4 ? t3 conducts. in the absence of flyback detection or if the flyback interval is longer than the blanking time, the sand- castle low level remains constant at 2.5v so as to protect the picture tube in the absence of frame scanning. - oifo signal is delivered by frame error amplifier (see frame phase modulator figure) - if is high during the frame flyback interval TEA2028 - tea2029 application note 38/46 blanking output s1 if blank' reset 24 lines normal operation too long flyback pulse (fr) 2028b-79.eps figure 76 blanking output to super sand castle 1 1 & & if if reset blk' blk' from frame counters q q s r r s q 2028b-78.eps figure 75 : frame blanking safety block diagram vii.6 - on-chip line flip-flop 26 m s v v v 16 in 10 df max = 16 m s 2028b-81.eps figure 78 16 13 c13 v in i f 2 16 m s window for dj max & 10 lf (line flyback) safety (pin 28) 1x1 s r q output 2028b-80.eps figure 77 t 10 =35 ? t vco -k ? r14 ? c13 =70 ? 10 -6 -4 ? r14 ? c13 where t vco is the v co period of oscillation on pin 18. - if in synchronized mode : t vco =2 m s, r14 = 3.32k w c13 = 3.3nf thereforet 10 = 26m s (nominal value) TEA2028 - tea2029 application note 39/46 4.7 m s burst video signal (pin 27) 2.3 m s 1.3 m s 0v 12v agc signal (pin 20) without video signal 2028b-82.eps figure 79 vii.7 - agc key pulse as illustrated below, this signal is used in some tv sets to perform sampling window for automatic gain control of picture demodulation network. this system is called oclampedo agc, and locks the demodulated line sync amplitude and hence sets the video signal amplitude. this signal generated by line logic circuitry is cor- rectly positioned by the first phase locked loop o f 1o and includes the line sync pulse of the video signal. this is an open-collector output. viii - application information on frame scanning in switched mode (tea2029 only) viii.1 - fundamentals (see figure 80) the secondary winding of eht transformer pro- vides the energy required by frame yoke. the frame current modulation is achieved by modulating the horizontal saw-tooth current and subsequent integration by a ol.co network to reject the horizontal frequency component. viii.2 - general description the basic circuit is the phase comparator oc 1 o which compares the horizontal saw-tooth and the output voltage of error amplifier oao. the comparator output will go ohigho when the horizontal saw-tooth voltage is higher than the oao output voltage. thus, the pin 4 output signal is switched in synchronization with the horizontal fre- quency and the duty cycle is modulated at frame frequency. a driver stage delivers the current required by the external power switch. the external thyristor provides for energy transfer between transformer and frame yoke. the thyristor will conduct during the last portion of horizontal trace phase and for half of the horizontal retrace. the inverse parallel-connected diode odo conducts during the second portion of horizontal retrace and at the beginning of horizontal trace phase. main advantages of this system are : - power thyristor soft oturn-ono once the thyristor has been triggered, the current gradually rises from 0 to ip, where ip will reach the maximum value at the end of horizontal trace. the slope current is determined by, the current available through the secondary winding, the yoke impedance and the ol.c.o filter charac- teristics. - power thyristor soft oturn-offo the secondary output current begins decreasing and falls to 0 at the middle of retrace. the thyristor is thus automatically oturned-offo. - excellent efficiency of power stage due to very low oturn-ono and oturn-offo switching losses. TEA2028 - tea2029 application note 40/46 viii.3 - typical frame modulator and frame output waveforms 1 2 4 r m 4.7 w c1 1000 m f +24v 120mh 60 w frame yoke 90 i y v c v b v control v lf v ref esm 740 d horizontal sawtooth i td l 500 m h eht transformer feedback frame amplitude adjust frame reference sawtooth (pin 3) tea2029c s c 0.47 m f 2028b-83.eps figure 80 : block diagram i i thyristor diode i td horizontal flyback thyristor gating signal horizontal sawtooth frame reference sawtooth beginning of frame trace end of frame trace 2028b-84.eps figure 81 TEA2028 - tea2029 application note 41/46 viii.4 - frame power stage waveforms 2028b-85.tif figure 82 2028b-86.tif figure 83 2028b-87.tif figure 84 2028b-88.tif figure 85 : different horizontal conducting times during frame 2028b-90.tif figure 87 2028b-89.tif figure 86 TEA2028 - tea2029 application note 42/46 the bias voltage ov b o is supplied by the secondary winding of eht transformer. the parabolic effect is due to the integration of frame saw-tooth by the filtering capacitor oc1o. dvb = i y ? t 8 ? c1 = 0.95v where : -i y : peak-to-peak yoke current = 380ma pp - t : 20ms - c1 = 1000 m f viii.5 - frame flyback during flyback, due to the loop time constant, the frame yoke current cannot be locked onto the reference saw-tooth. thus the output of amplifier oao will remain high and the thyristor is blocked. the scanning current will begin flowing through diode odo. as a consequence, the capacitor oco starts charging up to the flyback voltage. the thyris- tor is triggered as soon as the yoke current reaches the maximum positive value. eht transformer winding (see figure 88) (for 90 o tube : yoke ? l = 120mh, r y =60 w ) viii.6 - feed-back circuit viii.6.1 - frame power in quasi-bridge configu- ration (see figure 89) this stage measures the frame scanning current in differential mode and compares it to the reference saw-tooth on pin 3. the overall configuration is built around two sym- metrical networks : -or 1 ,r 2 ,r 3 o network : determines the dynamic saw-tooth voltage - or' 1 ,r' 2 ,r' 3 o network : sets the bias voltage and the d.c. shift control. a.c. gain : g = r 2 r 1 = i y v in ? a ? r m where : -i y : peak-to-peak yoke current -v in : peak-to-peak saw-tooth voltage (pin 3) - a [0,1] : amplitude adjustment viii.6.1.1 - choice of oro value the saw-tooth generator output is an emitter fol- lower stage. pin 3 output current must therefore be always negative. r< viii.6.1.3 - oso correction circuit in quasi-bridge configuration the oso correction waveform is obtained using the non-linear ov diode o versus oi diode o characteristics 3 2 1 v in r r1 v- c a r2 r3 v+ r'3 r'2 r'1 p2 v p v+ frame reference sawtooth v out p1 r m frame amplitude adjust a , r m .i y v b i y r m .i y frame yoke 2028b-92.eps figure 89 2 3 r1 r2 r r3 r5 220 w r4 2.2k w 100 w d2 d1 100 w r m v b yoke tea2029c 2028b-93.eps figure 90 of od1o and od2o diodes. the signal pre-corrected by od1o, od2o diodes and the feed-back signal through or5o, are summed at oao. the oso correction level is determined by the ratio between or4o and or5o resistors. viii.6.2 - frame scanning in switched mode using coupling capacitor (see figure 91) the parabolic voltage at (a) is integrated by or2, c2o network and used for oso correction. the oso waveform voltage at (b) is added to the saw-tooth voltage at(c). the oso levelis determined by oc2, r2, r3o network. 12 3 +v b 27k w frame swatooth 150k w 10k w r3 680k w r2 820k w linearity adjustment c2 0.1 m f 100 w 56k w vertical amplitude adjust 10 w c p (c) (a) (b) to safety input r4 r5 tea2029c 220k w yoke 2028b-94.eps figure 91 TEA2028 - tea2029 application note 44/46 viii.6.3 - frame safety in case of failure in the loop, the thyristor may remain turned-off while the inverse parallel-con- nected diode conducts. this will result in a haz- ardeous situation where the voltage across the coupling capacitor oc p o will reach an excessively high value. to avoid such situation, the voltage at point (a) should be applied to the osafetyo input pin 28 after it has gone through the matching network or4, r5o. viii.7 - frame scanning in class b with flyback generator viii.7.1 - application diagram 123 4 1 2 3 4 5 6 7 tda8172 1n4001 100 m f +24v 1nf 13k w 2.2k w 100nf tea2029c (pin 14) 33k w 10k w 15nf 150k w 680k w 470k w 470nf 2.7m w 200v 5 frame sawtooth 2.2k w 3.3k w 10k w +12v n.c. 100nf 15k w 100 w 1 w frame yoke 32mh 15 w 0.7app 1000 m f vertical phase shift 220 w vertical amplitude adjust tea2029c 2028b-95.eps figure 92 TEA2028 - tea2029 application note 45/46 ix - tea2029 application diagram complete application with tea2164 secondaryground (isolated from mains) ba157 313 6 20 19 7 9 21 7 6 4 5 12 13 16 11 10 2 9 8 3 14 1 tea216 4 15 100 w ba159 47 m f 100 w 330 w by218 100 m f 1000 m f 33k w 4 x 1n4007 fuse 1.6a 300k w 2x47 m f (385v) 100k w (2w) primaryground (connected to mains) 1.2nf 110k w 12k w 470k w 6.8 w 220 m f 1 2 2.2 w ba157 2.2 w 390 w 0.27 w 3 x 1n404 10 w 2 m h 2.2nf bu508a 220 w orega g.4173.04 22 by218 by218 470 m f 10k w tea2029c 24 20 7 22 19 18 15 27 26 25 12 11 28 5 3 1 2 6 4 10 21 9 8 14 13 23 16 17 2.2 m f 4.7 m f 1n4444 1.5nf 15nf 4.7 m f 3.9k w 220 w 503 khz 1.8k w 150pf 220 w 10 m f 470 w v cc 8.2k w 1n4148 5.6k w 5.6k w 15k w v cc agc pulse mute out & 50/60hz identification 100nf 220nf 4.7nf 100nf video input line flyback super sandcastle output 10k w 2.7m w 220k w 470nf 220 w 1k w 100nf 820 w 820 w 6.8k w 3.3k w 3.3k w 6.8k w 33 w 82k w 1k w 220 w 220 w 4.7 w 2.2k w e/w correction framephase adjust frame amplitude adjust 200v +24v v cc horizontalphase adjust 470k w 22nf vcr switch 3.3nf +25v 3.32k w (1%) 22nf 1k w 1.5k w 47nf 1nf esm 740 ba157 13v 27 w 680 w 2n1711 v cc 100nf 220 m f +135v / 0.6a 1k w 1k w 220pf 150k w smps output voltage adjust 220pf 100k w 390 w 1k w line yoke 0.47 m f frame yoke 120mh 60 w line flyback eht transformer 500 m h +200v +24v 220v mains input ac 1nf 330 w 2028b-96.eps figure 93 TEA2028 - tea2029 application note 46/46 information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no licence is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. sgs-thomson microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of sgs-thomson microelectronics. ? 1994 sgs-thomson microelectronics - all rights reserved purchase of i 2 c components of sgs-thomson microelectronics, conveys a license under the philips i 2 c patent. rights to use these components in a i 2 c system, is granted provided that the system conforms to the i 2 c standard specifications as defined by philips. sgs-thomson microelectronics group of companies australia - brazil - china - france - germany - hong kong - italy - japan - korea - malaysia - malta - morocco the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. |
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